74VHC32 ,QUAD 2-INPUT OR GATE74VHC32QUAD 2-INPUT OR GATE
74VHC32
QUAD 2-INPUT OR GATE
1/11November 2004 HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 2 μA (MAX.) at TA=25°C HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 32 IMPROVED LATCH-UP IMMUNITY LOW NOISE: V OLP = 0.8V (MAX.)
DESCRIPTIONThe 74VHC32 is an advanced high-speed CMOS
QUAD 2-INPUT OR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology.
The internal circuit is composed of 2 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC32QUAD 2-INPUT OR GATE
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 5
74VHC322/11
Figure 2: Input Equivalent Circuit Table 2: Pin Description
Table 3: Truth Table
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions 1) VIN from 30% to 70% of VCC
74VHC323/11
Table 6: DC Specifications
Table 7: AC Electrical Characteristics (Input tr = tf = 3ns) (*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
74VHC324/11
Table 8: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)
Table 9: Dynamic Switching Characteristics 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
Figure 3: Test Circuit CL =15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
74VHC325/11
Figure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
