74VHC273 ,Octal D-Type Flip-FlopGeneral Descriptionand two supply systems such as battery backup. This cir-The VHC273 is an advance ..
74VHC273FT ,74VHC CMOS logic IC seriesabsolute maximum ratings, even briefly, lead to deterioration in IC performance or evendestruction. ..
74VHC273M ,Octal D-Type Flip-Flop74VHC273 Octal D-Type Flip-FlopApril 1994Revised May 200374VHC273Octal D-Type Flip-Flop
74VHC273M ,Octal D-Type Flip-FlopFeaturesThe VHC273 is an advanced high speed CMOS Octal
74VHC273
Octal D-Type Flip-Flop
74VHC273 Octal D-Type Flip-Flop April 1994 Revised April 1999 74VHC273 Octal D-Type Flip-Flop age. This device can be used to interface 5V to 3V systems General Description and two supply systems such as battery backup. This cir- The VHC273 is an advanced high speed CMOS Octal D- cuit prevents device destruction due to mismatched supply type flip-flop fabricated with silicon gate CMOS technology. and input voltages. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low Features power dissipation. � High Speed: f = 165 MHz (typ) at V = 5V The register has a common buffered Clock (CP) which is MAX CC fully edge-triggered. The state of each D input, one setup � Low power dissipation: I = 4 μA (max) at T = 25°C CC A time before the LOW-to-HIGH clock transition, is trans- � High noise immunity: V = V = 28% V (min) NIH NIL CC ferred to the corresponding flip-flop’s Q output. The Master � Power down protection is provided on all inputs Reset (MR) input will clear all flip-flops simultaneously. All outputs will be forced LOW independently of Clock or Data � Low noise: V = 0.9V (max) OLP inputs by a LOW voltage level on the MR input. � Pin and function compatible with 74HC273 An input protection circuit insures that 0V to 7V can be applied to the inputs pins without regard to the supply volt- Ordering Code: Order Number Package Number Package Description 74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D –D Data Inputs 0 7 Master Reset MR CP Clock Pulse Input Q –Q Data Outputs 0 7 © 1999 DS011670.prf
