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74VHC257M
QUAD 2 CHANNEL MULTIPLEXER (3-STATE)
1/11June 2001 HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 4 μA (MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 8mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 257 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (MAX.)
DESCRIPTIONThe 74VHC257 is an advanced high-speed
CMOS QUAD 2-CHANNEL MULTIPLEXER
(3-STATE) fabricated with sub-micron silicon gate
and double-layer metal wiring C2 MOS technology.
It is composed of four independent 2-channel
multiplexers with common SELECT and ENABLE
(OE) INPUT. The VHC257 is a non-inverting
multiplexer. When the ENABLE INPUT is held
"High", all outputs become in high impedance
state. If SELECT INPUT is held "Low", "A" data is
selected, when SELECT INPUT is "High", "B"
data is chosen.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC257QUAD 2 CHANNEL MULTIPLEXER (3-STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74VHC2572/11
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Z : High Impedance
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74VHC2573/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74VHC2574/11
DC SPECIFICATIONS
74VHC2575/11
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per
channel)
74VHC2576/11
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
TEST CIRCUIT CL =15/ 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
