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74VHC244TTR
OCTAL BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED)
74VHC244OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (NON INVERTED)
June 1999 HIGH SPEED: tPD = 3.9 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 4 μA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 244 IMPROVED LATCH-UP IMMUNITY LOW NOISE VOLP = 0.9V (Max.)
DESCRIPTION The 74VHC244 is an advanced high speed
CMOS OCTAL BUS BUFFER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS technology.
G output enable governs four BUS BUFFERs.
This device is designed to be used with 3 state
memory address drivers, etc.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS1/8
INPUT EQUIVALENT CIRCUIT
TRUTH TABLEX: "H" or "L"
Z: High impedance
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS1) VIN from 30% to 70% of VCC
74VHC2442/8
AC ELECTRICAL CHARACTERISTICS (Input tr = tf =3 ns)(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5V ± 0.5V
Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
DC SPECIFICATIONS
74VHC2443/8
CAPACITIVE CHARACTERISTICS1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/48(per Gate)
TEST CIRCUITCL = 15/50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
74VHC2444/8
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
74VHC2445/8
74VHC2446/8
