74VHC02MTCX ,Quad 2-Input NOR GateFeaturesThe VHC02 is an advanced high-speed CMOS 2-Input
74VHC02M-74VHC02MTC-74VHC02MTCX-74VHC02MX-74VHC02SJ
Quad 2-Input NOR Gate
74VHC02 Quad 2-Input NOR Gate November 1992 Revised February 2005 74VHC02 Quad 2-Input NOR Gate General Description Features The VHC02 is an advanced high-speed CMOS 2-InputHigh Speed: t 3.6 ns (typ) at V 5V PD CC NOR Gate fabricated with silicon gate CMOS technology. It Low power dissipation: I 2 PA (max) at T 25qC CC A achieves the high-speed operation similar to equivalent High noise immunity: V V 28% V (min) Bipolar Schottky TTL while maintaining the CMOS low NIH NIL CC power dissipation. The internal circuit is composed of 3Power down protection is provided on all inputs stages, including buffer output, which provide high noise Low noise: V 0.8V (max) OLP immunity and stable output. An input protection circuit Pin and function compatible with 74HC02 insures that 0V to 7V can be applied to the input pins with- out regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Code: Package Order Number Package Description Number 74VHC02M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC02MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow (Note 1) 74VHC02SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC02MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC02MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide 74VHC02N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol Connection Diagram IEEE/IEC Truth Table AB O Pin Descriptions LL H Pin Names Description LH L A , B Inputs HL L n n O Outputs HH L n © 2005 DS011515
