74VHC00MTCX ,Quad 2-Input NAND GateFeaturesThe VHC00 is an advanced high-speed CMOS 2-Input
74VHC00M-74VHC00MTC-74VHC00MTCX-74VHC00MX-74VHC00N-74VHC00SJ-74VHC00SJX
Quad 2-Input NAND Gate
74VHC00 Quad 2-Input NAND Gate October 1992 Revised February 2005 74VHC00 Quad 2-Input NAND Gate General Description Features The VHC00 is an advanced high-speed CMOS 2-InputHigh Speed: t 3.7ns (typ) at T 25qC PD A NAND Gate fabricated with silicon gate CMOS technology. High noise immunity: V V 28% V (min) NIH NIL CC It achieves the high-speed operation similar to equivalent Power down protection is provided on all inputs Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3Low noise: V 0.8V (max) OLP stages, including buffer output, which provide high noise Low power dissipation: I 2 PA (max) at T 25qC CC A immunity and stable output. An input protection circuit Pin and function compatible with 74HC00 insures that 0V to 7V can be applied to the input pins with- out regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Code: Package Order Number Package Description Number 74VHC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC00MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC00SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC00MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide 74VHC00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol Connection Diagram IEEE/IEC Truth Table Pin Descriptions AB O LL H Pin Names Description LH H A , B Inputs n n HL H O Outputs n HH L © 2005 DS011504
