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74VCXHQ163245R-E
16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH BUS HOLD AND EMI NOISE CONTROL
1/17January 2005 HIGH SPEED: tPD =6.0ns (MAX.) at TA =85°C CCA = 3.0V V CCB = 2.3V; Bn to An LOW POWER DISSIPATION:
ICCA = ICCB = 20µA(MAX.) at TA=85°C SYMMETRICAL OUTPUT IMPEDANCE: OHA | = I OLA = 2.6mA MIN at CCA = 3.0V; V CCB = 1.65V or 2.3V
|IOHB| = IOLB = 6mA (MIN at CCA = 2.3V or 3.0V; V CCB = 1.65V) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SERIES RESISTOR ON A SIDE LIMITED EMI NOISE: trA ≅ tfA ≥ 4ns at
CL =10pF OPERATING VOLTAGE RANGE:
VCCA(OPR) = 2.3V to 3.6V (1.2V Data
Retention) CCB (OPR) = 1.65V to 3.6V (1.2V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16245 BUS HOLD PROVIDED ON DATA INPUT
BOTH SIDE LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74VCXHQ163245 is a dual supply low
voltage CMOS 16-BIT BUS TRANSCEIVER
fabricated with sub-micron silicon gate and
five-layer metal wiring C2 MOS technology.
Designed for use as an interface between a 3.3V
bus and a 2.5V or 1.8V bus in a mixed 3.3V/
1.8V,3.3V/2.5V and 2.5V/1.8V supply systems, it
achieves high speed operation while maintaining
the CMOS low power dissipation and limited rise
and fall time (Low EMI).
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
nDIR inputs. The enable inputs nG can be used to
disable the device so that the buses are effectively
isolated. The A-port interfaces with the 3V bus, the
B-port with the 2.5V and 1.8V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage. All floating
bus terminals during High Z State don’t need
external pull-up or pull-down resistor.
74VCXHQ163245 16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL
TRANSLATOR WITH BUS HOLD AND EMI NOISE CONTROL
Table 1: Order Codes (*) Lead-Free Compliant.
Figure 1: Logic DiagramRev. 3
74VCXHQ1632452/17
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
74VCXHQ1632453/17
Figure 3: Pin Connection (top view for TSSOP, top through view for BGA)
Table 3: Truth Table X=Don’t care; Z=High Impedance
74VCXHQ1632454/17
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those value beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions 1) VIN from 0.8V to 2.0V at VCC =3.0V
74VCXHQ1632455/17
Table 6: DC Specification For V CCA (*) VCC range = 3.3±0.3; 2.5±0.2V; 1.8±0.15V
74VCXHQ1632456/17
Table 7: DC Specification For V CCB (*) VCC range = 3.3±0.3; 2.5±0.2V; 1.8±0.15V
74VCXHQ1632457/17
Table 8: Dynamic Switching Characteristics
Table 9: AC Electrical Characteristics (CLA = 10pF, CLB = 30pF, RL = 500Ω) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|
2) Parameter guaranteed by design
74VCXHQ1632458/17
Table 10: Capacitance Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit)
Figure 4: Test Circuit CL = 10/30pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Table 11: Waveform Symbol Value
74VCXHQ1632459/17
Figure 5: Waveform - Propagation Delay (f=1MHz; 50% duty cycle)
Figure 6: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)
