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74VCXH16240DT
Low-Voltage 1.8/2.5/3.3V 16-Bit Buffer
74VCXH16240
Low-Voltage 1.8/2.5/3.3V
16-Bit Buffer
With 3.6 V −T olerant Inputs and Outputs
(3−State, Inverting)The 74VCXH16240 is an advanced performance, inverting 16−bit
buffer. It is designed for very high−speed, very low−power operation
in 1.8 V , 2.5 V or 3.3 V systems.
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V.
The 74VCXH16240 is nibble controlled with each nibble
functioning identically, but independently. The control pins may be
tied together to obtain full 16−bit operation. The 3−state outputs are
controlled by an Output Enable (OEn) input for each nibble. When
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are
in the high impedance state. The data inputs include active bushold
circuitry, eliminating the need for external pullup resistors to hold
unused or floating inputs at a valid logic state.
Features Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V 3.6 V Tolerant Inputs and Outputs High Speed Operation: 2.5 ns max for 3.0 V to 3.6 V
3.0 ns max for 2.3 V to 2.7 V
6.0 ns max for 1.65 V to 1.95 V Static Drive: ±24 mA Drive at 3.0 V
±18 mA Drive at 2.3 V
±6 mA Drive at 1.65 V Supports Live Insertion and Withdrawal Includes Active Bushold to Hold Unused or Floating Inputs at a alid Logic State IOFF Specification Guarantees High Impedance When VCC = 0 V* Near Zero Static Supply Current in All Three Logic States (20 �A)
Substantially Reduces System Power Requirements Latchup Performance Exceeds ±250 mA @ 125°C ESD Performance: Human Body Model >2000 V
Machine Model >200 V All Devices in Package TSSOP are Inherently Pb−Free**
*To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to VCC through a pullup resistor. The value of the resistor
is determined by the current sinking capability of the output connected to the
OE pin.
**For additional information on our Pb−Free strategy and soldering details,
MARKING DIAGRAM = Assembly Location = Wafer Lot = Year = Work Week
TSSOP−48
DT SUFFIX
CASE 1201 11
ORDERING INFORMATION†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
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