74VCX16839MTD ,Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and OutputsFunctional DescriptionThe 74VCX16839 consists of twenty selectable non-invert-ing buffers or regist ..
74VCX16839MTD ,Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs74VCX16839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and OutputsJuly ..
74VCX16839MTDX ,Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and OutputsFunctional DescriptionThe 74VCX16839 consists of twenty selectable non-invert-ing buffers or regist ..
74VCX16839MTDX ,Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputsapplications with I/O compatibility up to 3.6V.
74VCX16839MTD-74VCX16839MTDX
Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
74VCX16839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs July 1997 Revised November 2000 74VCX16839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16839 contains twenty non-inverting selectableCompatible with PC100 and PC133 DIMM module buffered or registered paths. The device can be configured specifications to operate in a registered, or flow through buffer mode by1.65V–3.6V V supply operation CC utilizing the register enable (REGE) and Clock (CLK) sig- 3.6V tolerant inputs and outputs nals. The device operates in a 20-bit word wide mode. All t (CLK to O ) outputs can be placed into 3-STATE through use of the OE PD n pin. These devices are ideally suited for buffered or regis- 3.2 ns max for 3.0V to 3.6V V CC tered 168 pin and 200 pin SDRAM DIMM memory mod- 4.4 ns max for 2.3V to 2.7V V CC ules. 8.8 ns max for 1.65V to 1.95V V The 74VCX16839 is designed for low voltage (1.65V to CC 3.6V) V applications with I/O compatibility up to 3.6V.Power-off high impedance inputs and outputs CC The 74VCX16839 is fabricated with an advanced CMOSSupports live insertion and withdrawal (Note 1) technology to achieve high speed operation while maintain-Static Drive (I /I ) OH OL ing low CMOS power dissipation. ±24 mA @ 3.0V V CC ±18 mA @ 2.3V V CC ±6 mA @ 1.65V V CC Uses patented noise/EMI reduction circuitry Latch-up performance exceeds 300 mA ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Descriptions 74VCX16839MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) I –I Inputs 0 19 O –O Outputs 0 19 CLK Clock Input REGE Register Enable Input © 2000 DS500105
