74VCX16601 ,Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and OutputsFeaturesThe VCX16601 is an 18-bit universal bus transceiver which
74VCX16601
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs March 1998 Revised August 2001 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16601 is an 18-bit universal bus transceiver which1.65V–3.6V V supply operation CC combines D-type latches and D-type flip-flops to allow data 3.6V tolerant inputs and outputs flow in transparent, latched, and clocked modes. t (A to B, B to A) PD Data flow in each direction is controlled by output-enable 2.9 ns max for 3.0V to 3.6V V (OEAB and OEBA), latch-enable (LEAB and LEBA), and CC clock (CLKAB and CLKBA) inputs. The clock can be con- 3.5 ns max for 2.3V to 2.7V V CC trolled by the clock-enable (CLKENAB and CLKENBA) 7.0 ns max for 1.65V 1.95V V CC inputs. For A-to-B data flow, the device operates in the Power-down high impedance inputs and outputs transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-to-Supports live insertion/withdrawal (Note 1) LOW logic level. If LEAB is LOW, the A bus data is stored Static Drive (I /I ) OH OL in the latch/flip-flop on the LOW-to-HIGH transition of ±24 mA @ 3.0V V CLKAB. When OEAB is LOW, the outputs are active. When CC OEAB is HIGH, the outputs are in the high-impedance ±18 mA @ 2.3V V CC state. ±6 mA @ 1.65V V CC Data flow for B to A is similar to that of A to B but uses Uses patented noise/EMI reduction circuitry OEBA, LEBA, CLKBA and CLKENBA. Latchup performance exceeds 300 mA The VCX16601 is designed for low voltage (1.65V to 3.6V) ESD performance: V applications with I/O capability up to 3.6V. CC Human body model > 2000V The VCX16601 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- Machine model >200V ing low CMOS power dissipation.Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74VCX16601GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 2) (Preliminary) [TAPE and REEL] 74VCX16601MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 DS500126
