74VCX164245MTD ,Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs74VCX164245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE OutputsMarch 2000Re ..
74VCX16500MTD ,Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and OutputsFeaturesThe VCX16500 is an 18-bit universal bus transceiver which
74VCX164245G-74VCX164245MTD
Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
74VCX164245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs March 2000 Revised August 2003 74VCX164245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs General Description Features The VCX164245 is a dual supply, 16-bit translating trans-Bidirectional interface between busses ranging from ceiver that is designed for two way asynchronous commu- 1.65V to 3.6V nication between busses at different supply voltages bySupports Live Insertion and Withdrawal (Note 1) providing true signal translation. The supply rails consist of Static Drive (I /I ) OH OL V , which is the higher potential rail operating at 2.3V to CCB ±24 mA @ 3.0V V CC 3.6V and V , which is the lower potential rail operating at CCA 1.65V to 2.7V. (V must be less than or equal to V ±18 mA @ 2.3V V CCA CCB CC for proper device operation.) This dual supply design ±6 mA @ 1.65V V CC allows for translation from 1.8V to 2.5V busses to busses at Uses patented noise/EMI reduction circuitry a higher potential, up to 3.3V. Functionally compatible with 74 series 16245 The Transmit/Receive (T/R) input determines the direction Latchup performance exceeds 300 mA of data flow. Transmit (active-HIGH) enables data from A Ports to B Ports. Receive (active-LOW) enables data fromESD performance: B Ports to A Ports. The Output Enable (OE) input, when Human Body Model >2000V HIGH, disables both A and B Ports by placing them in a Machine model >200V High-Z condition. The A Port interfaces with the lower volt- Also packaged in plastic Fine-Pitch Ball Grid Array age bus (1.8V − 2.5V). The B Port interfaces with the (FBGA) higher voltage bus (2.7V − 3.3V). Also the VCX164245 is designed so that the control pins (T/R , OE ) are supplied n n by V . CCB Note 1: To ensure the high impedance state during power up or power The 74VCX164245 is suitable for mixed voltage applica- down, OE should be tied to V through a pull up resistor. The minimum n CCB tions such as notebook computers using a 1.8V CPU and value of the resistor is determined by the current sourcing capability of the 3.3V peripheral components. It is fabricated with an driver. Advanced CMOS technology to achieve high speed opera- tion while maintaining low CMOS power dissipation. Ordering Code: Order Number Package Number Package Description 74VCX164245G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 2)(Note 3) 74VCX164245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 3) Note 2: Ordering Code “G” indicates Trays. Note 3: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Diagram © 2003 DS500159
