74VCX16373 ,Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputsapplications with I/O compatibility up to 3.6V. ±24 mA @ 3.0V VCC CCThe 74VCX16373 is fabricated wi ..
74VCX16373DTR ,Low-Voltage 1.8/2.5/3.3V 16-Bit Transparent LatchFeaturesO0−O15 Outputs• Designed for Low Voltage Operation: V = 1.65 V − 3.6 VCC• 3.6 V Tolerant In ..
74VCX16373MTD ,Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputsapplications with I/O compatibility up to 3.6V. ±24 mA @ 3.0V VCC CCThe 74VCX16373 is fabricated wi ..
74VCX16373MTDX ,Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and OutputsFeaturesThe VCX16373 contains sixteen non-inverting latches with
74VCX16373
Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74VCX16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs October 1997 Revised November 2001 74VCX16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16373 contains sixteen non-inverting latches with � 1.4V to 3.6V V supply operation CC 3-STATE outputs and is intended for bus oriented applica- � 3.6V tolerant inputs and outputs tions. The device is byte controlled. The flip-flops appear to � t (I to O ) PD n n be transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time 3.0 ns max for 3.0V to 3.6V V CC is latched. Data appears on the bus when the Output � Power-off high impedance inputs and outputs Enable (OE) is LOW. When OE is HIGH, the outputs are in � Support live insertion and withdrawal (Note 1) a high impedance state. � Static Drive (I /I ) OH OL The 74VCX16373 is designed for low voltage (1.4V to 3.6V) V applications with I/O compatibility up to 3.6V. ±24 mA @ 3.0V V CC CC The 74VCX16373 is fabricated with an advanced CMOS � Uses patented noise/EMI reduction circuitry technology to achieve high speed operation while maintain- � Latch-up performance exceeds 300 mA ing low CMOS power dissipation. � ESD performance: Human body model > 2000V Machine model > 200V � Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74VCX16373GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 2) (Preliminary) [TAPE and REEL] 74VCX16373MTD 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide MTD48 (Note 3) Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2001 DS500065
