74VCX162601MTDX ,Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in the B-Port Outputsapplications such as memory address drivers, clock driv-ers, and bus transceivers/transmitters. Ord ..
74VCX162827MTD ,Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in the OutputsFeaturesThe VCX162827 contains twenty non-inverting buffers with
74VCX162601MTDX
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Ohm Series Resistors in the B-Port Outputs
74VCX162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the B-Port Outputs April 1998 Revised October 2004 74VCX162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the B-Port Outputs General Description Features The VCX162601, 18-bit universal bus transceiver, com-1.4V to 3.6V V supply operation CC bines D-type latches and D-type flip-flops to allow data flow 3.6V tolerant inputs and outputs in transparent, latched, and clocked modes. 26Ω series resistors in B-Port outputs Data flow in each direction is controlled by output-enable t (A to B) PD (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be con- 3.8 ns max for 3.0V to 3.6V V CC trolled by the clock-enable (CLKENAB and CLKENBA) Power-down high impedance inputs and outputs inputs. For A-to-B data flow, the device operates in the Supports live insertion/withdrawal (Note 1) transparent mode when LEAB is HIGH. When LEAB is Static Drive (I /I B outputs) LOW, the A data is latched if CLKAB is held at a HIGH-to- OH OL LOW logic level. If LEAB is LOW, the A bus data is stored ±12 mA @ 3.0V V CC in the latch/flip-flop on the LOW-to-HIGH transition of Uses patented noise/EMI reduction circuitry CLKAB. Output-enable OEAB is active-LOW. When OEAB Latchup performance exceeds 300 mA is HIGH, the outputs are in the HIGH-impedance state. ESD performance: Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. Human body model > 2000V The 74VCX162601 is designed for low voltage (1.4V to Machine model >200V 3.6V) V applications with I/O compatibility up to 3.6V. CC Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum The VCX162601 is also designed with 26Ω series resistors CC value of the resistor is determined by the current-sourcing capability of the in the B-Port outputs. This design reduces line noise in driver. applications such as memory address drivers, clock driv- ers, and bus transceivers/transmitters. Ordering Code: Order Number Package Number Package Description 74VCX162601MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Pin Names Description OEAB, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs A –A Side A Inputs or 3-STATE Outputs 1 18 B –B Side B Inputs or 3-STATE Outputs 1 18 © 2004 DS500150
