74VCX16240MTDX ,Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputsapplications with I/O capability up to 3.6V.CC
74VCX16240MTD-74VCX16240MTDX
Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
74VCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs January 1998 Revised October 2004 74VCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16240 contains sixteen inverting buffers with1.2V to 3.6V V supply operation CC 3-STATE outputs to be employed as a memory and 3.6V tolerant inputs and outputs address driver, clock driver, or bus oriented transmitter/ t PD receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted 2.5 ns max for 3.0V to 3.6V V CC together for full 16-bit operation. Power-off high impedance inputs and outputs The 74VCX16240 is designed for low voltage (1.2V to Supports live insertion and withdrawal (Note 1) 3.6V) V applications with I/O capability up to 3.6V. CC Static Drive (I /I ) OH OL The 74VCX16240 is fabricated with an advanced CMOS ±24 mA @ 3.0V V CC technology to achieve high speed operation while maintain- ing low CMOS power dissipation.Uses patented noise/EMI reduction circuitry Latch-up performance exceeds 300 mA ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Descriptions 74VCX16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n I –I Inputs 0 15 O –O Outputs 0 15 © 2004 DS500099
