74V2T08STR ,DUAL 2-INPUT AND GATE74V2T08DUAL 2-INPUT AND GATE ■ HIGH SPEED: t = 3.8ns (TYP.) at V = 5VPD CC■ LOW POWER DISSIPATION: ..
74V2T125STR ,DUAL BUS BUFFER (3-STATE)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74V2T126STR ,DUAL BUS BUFFER (3-STATE)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74V2T14STR ,TRIPLE SHMITT INVERTERAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74V2T32STR ,DUAL 2-INPUT OR GATE74V2T32DUAL 2-INPUT OR GATEPRELIMINARY DATA ■ HIGH SPEED: t = 4.6ns (TYP.) at V = 5VPD CC■ LOW POW ..
74V2T66STR ,DUAL BILATERAL SWITCHAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
87705-0021 , 1.00mm (.039") Pitch DDR-II DIMM Socket, Vertical, Center Keys, 2.67mm (.105") Tail Length, Beige Latches
87832-1420 , 2.00mm (.079) Pitch Milli-Grid™ Header, Surface Mount, Vertical, Shrouded, Leadfree 14 Circuits, 0.38μm (15μ) Gold (Au) Plating
87C451 ,80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
87C451 ,80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
87C51 ,MCS 51 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
87C51 ,MCS 51 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
74V2T08STR
DUAL 2-INPUT AND GATE
1/9May 2002 HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 1μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN) VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 8mA (MIN) at VCC = 4.5V BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74V2T08 is an advanced high-speed CMOS
DUAL 2-INPUT AND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS tecnology.
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage.
This device can be used to interface 5V to 3V.
74V2T08DUAL 2-INPUT AND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74V2T082/9
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) VIN from 0.8 to 2V
74V2T083/9
DC SPECIFICATION
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) (*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITANCE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivqlent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average current cqn be obtqined by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2
74V2T084/9
TEST CIRCUIT CL = 15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAY (f=1MHz; 50% duty cycle)
74V2T085/9
74V2T086/9
