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74V2G05STR
TRIPLE INVERTER (OPEN DRAIN)
1/9November 2001 HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:
ICC = 1μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUT OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74V2G05 is an advanced high-speed CMOS
TRIPLE INVERTER (OPEN DRAIN) fabricated
with sub-micron silicon gate and double-layer
metal wiring C2 MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on input and 0
to 7V can be accepted on input with no regard to
the supply voltage. This device can be used to
interface 5V to 3V.
74V2G05TRIPLE INVERTER (OPEN DRAIN)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PRELIMINARY DATA
74V2G052/9
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE Z: High Impedance
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74V2G053/9
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
74V2G054/9
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/3
TEST CIRCUIT CL = 15/50pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAY (f=1MHz; 50% duty cycle)
74V2G055/9
74V2G056/9
