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74V2G02STR
DUAL 2-INPUT NOR GATE
1/9October 2002 HIGH SPEED:tPD= 3.6ns (TYP.)atVCC =5V LOW POWER DISSIPATION:
ICC =1μA(MAX.)at TA=25°C HIGH NOISE IMMUNITY:
VNIH =VNIL= 28% VCC (MIN.) POWER DOWN PROTECTIONON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL =8mA (MIN)at VCC =4.5V BALANCED PROPAGATION DELAYS:
tPLH≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR)=2Vto 5.5V IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74V2G02isan advanced high-speed CMOS
DUAL 2-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiringC2 MOS technology.
The internal circuitis composedof3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protectionis providedonall inputs
and0to7V canbe acceptedon inputs withno
regardtothe supply voltage. This device canbe
usedto interface5Vto3V.
74V2G02DUAL 2-INPUT NOR GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74V2G022/9
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not implied..
RECOMMENDED OPERATING CONDITIONSVINfrom30%to70%ofVCC
74V2G023/9
SPECIFICATIONS ELECTRICAL CHARACTERISTICS (Inputtr=tf =3ns)
(*) Voltage rangeis3.3V±0.3V
(**) Voltage rangeis5.0V±0.5V
CAPACITIVE CHARACTERISTICSCPD isdefinedasthe valueoftheIC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load. (RefertoTest Circuit). Average operating currentcanbe obtainedbythe following equation. ICC(opr) =CPD xVCCxfIN +ICC/2
74V2G024/9
TEST CIRCUIT= 15/50pFor equivalent (includesjigand probe capacitance) =ZOUTof pulse generator (typically50Ω)
WAVEFORM: PROPAGATION DELAY (f=1MHz; 50% duty cycle)
74V2G025/9
74V2G026/9
