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74LX1G05CTR
LOW VOLTAGE SINGLE INVERTER (OPEN DRAIN)
1/10March 2002 5V TOLERANT INPUTS HIGH SPEED: tPD = 4.2ns (MAX.) at VCC = 3V LOW POWER DISSIPATION:
ICC = 1μA (MAX.) at TA = 25°C POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS OPERATING VOLTAGE RANGE:CC (OPR) = 1.65V to 5.5V
(1.2V Data Retention) IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LX1G05 is a low voltage CMOS SINGLE
INVERTER (OPEN DRAIN) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
This device can also be used as a led driver in any
other application requiring current sink.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge.
74LX1G05SINGLE INVERTER OPEN DRAIN
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LX1G052/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION TRUTH TABLE Z: High Impedance
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND, VO > VCC
74LX1G053/10
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
DC SPECIFICATIONS
74LX1G054/10
AC ELECTRICAL CHARACTERISTICS
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
74LX1G055/10
TEST CIRCUIT RT = ZOUT of pulse generator (typically 50Ω)
TEST CIRCUIT AND WAVEFORM SYMBOL VALUE
WAVEFORM: PROPAGATION DELAY (f=1MHz; 50% duty cycle)
