74LVXZ161284 ,Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection74LVXZ161284 Low Voltage IEEE 161284 Translating Transceiver with Power-Up ProtectionMay 2002Revise ..
74LVXZ161284MTX , Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection
74LVXZ161284MTX , Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection
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74LVXZ161284
Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection
74LVXZ161284 Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection May 2002 Revised May 2002 74LVXZ161284 Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection General Description Features The LVXZ161284 contains eight bidirectional data buffers � Supports IEEE 1284 Level 1 and Level 2 signaling and eleven control/status buffers to implement a full standards for bidirectional parallel communications IEEE 1284 compliant interface. The device supports the between personal computers and printing peripherals IEEE 1284 standard and is intended to be used in an � Translation capability allows outputs on the cable side to Extended Capabilities Port mode (ECP). The pinout allows interface with 5V signals for easy connection from the Peripheral (A-side) to the � All inputs have hysteresis to provide noise margin Host (cable side). � B and Y output resistance optimized to drive external Outputs on the cable side can be configured to be either cable open drain or high drive (± 14 mA) and are connected to a � B and Y outputs in high impedance mode during power separate power supply pin (V ) that allows these CC-Cable down outputs to be driven by a higher supply voltage than � C inputs and B, Y outputs on cable side have internal 1.4 the A-side. The pull-up and pull-down series termination kΩ pull-up resistors resistance of these outputs on the cable side is optimized to drive an external cable. In addition, the C inputs and the � Flow-through pin configuration allows easy interface B and Y outputs on the cable side contain internal pull-up between the “Peripheral and Host” resistors connected to the V supply to provide CC-Cable � Replaces the function of two (2) 74ACT1284 devices proper input termination and pull-ups for open drain output � Power-up protection prevents errors when the printer is mode. powered on but no valid signal is at the input pins Outputs on the Peripheral side are standard low-drive (A - A ). 9 13 CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A –A /B –B transceiver 1 8 1 8 pins. This device also has an added power-up protection feature which forces the Y outputs (Y - Y ) to a high state after 9 13 power-on until one of the associated inputs (A - A ) goes 9 13 HIGH. When an associated input (A - A ) goes HIGH, all 9 13 Y outputs (Y - Y ) are activated. 9 13 Ordering Code Package Order Number Package Description Number 74LVXZ161284MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [RAIL] 74LVXZ161284MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LVXZ161284MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [RAIL] 74LVXZ161284MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] © 2002 DS500729
