74LVX74MX ,Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-FlopMay 1993Revised February 200574LVX ..
74LVX74MX ,Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flopapplications
74LVX74M-74LVX74MTCX-74LVX74MX-74LVX74SJ
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop May 1993 Revised February 2005 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Asynchronous Inputs: General Description LOW input to S (Set) sets Q to HIGH level D The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. LOW input to C (Clear) sets Q to LOW level D Information at the input is transferred to the outputs on the Clear and Set are independent of clock positive edge of the clock pulse. After the Clock Pulse input Simultaneous LOW on C and S makes both Q and Q D D threshold voltage has been passed, the Data input is locked out and information present will not be transferred to HIGH the outputs until the next rising edge of the Clock Pulse input. Features Input voltage level translation from 5V to 3V Ideal for low power/low noise 3.3V applications Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Package Order Number Package Description Number 74LVX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVX74MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Connection Diagram Pin Descriptions Pin Names Description D , D Data Inputs 1 2 CP , CP Clock Pulse Inputs 1 2 C , C Direct Clear Inputs D1 D2 S , S Direct Set Inputs D1 D2 Q , Q , Q , Q Outputs 1 1 2 2 © 2005 DS011606
