74LVX373MTCX ,Low Voltage Octal Transparent Latch with 3-STATE Outputs74LVX373 Low Voltage Octal Transparent Latch with 3-STATE OutputsJune 1993Revised September 200374L ..
74LVX373MTCX ,Low Voltage Octal Transparent Latch with 3-STATE OutputsFunctional DescriptionThe LVX373 contains eight D-type latches with 3-STATE sition of LE. The 3-STA ..
74LVX373MTCX ,Low Voltage Octal Transparent Latch with 3-STATE Outputsapplications. The latches appear
74LVX373M-74LVX373MTC-74LVX373MTCX
Low Voltage Octal Transparent Latch with 3-STATE Outputs
74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs June 1993 Revised September 2003 74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVX373 consists of eight latches with 3-STATE outputsInput voltage translation from 5V to 3V for bus organized system applications. The latches appearIdeal for low power/low noise 3.3V applications transparent to the data when Latch Enable (LE) is HIGH. Guaranteed simultaneous switching noise level and When LE is LOW, the data satisfying the input timing dynamic threshold performance requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems. Ordering Code: Order Number Package Number Package Description 74LVX373M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Pin Descriptions Pin Names Description D –D Data Inputs 0 7 LE Latch Enable Input OE Output Enable Input IEEE/IEC O –O 3-STATE Latch Outputs 0 7 Truth Table Inputs Outputs LE OE D O n n XH X Z HL L L HL H H Connection Diagram LL X O 0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O = Previous O before HIGH-to-LOW transition of Latch Enable 0 0 © 2003 DS011613
