74LVX32MTCX ,Low Voltage Quad 2-Input OR Gate74LVX32 Low Voltage Quad 2-Input OR GateMay 1993Revised February 200574LVX32Low Voltage Quad 2-Inpu ..
74LVX32MTCX ,Low Voltage Quad 2-Input OR Gateapplicationstems to 3V systems.
74LVX32M-74LVX32MTC-74LVX32MTCX-74LVX32MX-74LVX32SJX
Low Voltage Quad 2-Input OR Gate
74LVX32 Low Voltage Quad 2-Input OR Gate May 1993 Revised February 2005 74LVX32 Low Voltage Quad 2-Input OR Gate General Description Features The LVX32 contains four 2-input OR gates. The inputs tol-Input voltage level translation from 5V to 3V erate voltages up to 7V allowing the interface of 5V sys-Ideal for low power/low noise 3.3V applications tems to 3V systems. Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Package Order Number Package Description Number 74LVX32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX32MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow (Note 1) 74LVX32SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX32MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVX32MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol Connection Diagram IEEE/IEC Pin Description Pin Names Description A , B Inputs n n O Outputs n © 2005 DS011604
