74LVX273MTC ,Low Voltage Octal D-Type Flip-FlopFeaturesThe LVX273 has eight edge-triggered D-type flip-flops with
74LVX273M-74LVX273MTC-74LVX273MTCX-74LVX273MX-74LVX273SJX
Low Voltage Octal D-Type Flip-Flop
74LVX273 Low Voltage Octal D-Type Flip-Flop June 1993 Revised September 2003 74LVX273 Low Voltage Octal D-Type Flip-Flop General Description Features The LVX273 has eight edge-triggered D-type flip-flops withInput voltage translation from 5V to 3V individual D inputs and Q outputs. The common bufferedIdeal for low power/low noise 3.3V applications Clock (CP) and Master Reset (MR) input load and reset Guaranteed simultaneous switching noise level and (clear) all flip-flops simultaneously. dynamic threshold performance The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transi- tion, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems. Ordering Code: Order Number Package Number Package Description 74LVX273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Truth Table Pin Descriptions Operating Mode Inputs Outputs D Q Pin Names Description MR CP n n D –D Data Inputs 0 7 Reset (Clear) L X X L MR Master Reset Load '1' HHH CP Clock Pulse Input Load '0' HLL Q –Q Data Outputs H = HIGH Voltage Level X = Immaterial 0 7 L = LOW Voltage Level = LOW-to-HIGH Transition © 2003 DS011614
