74LVX240MX ,Low Voltage Octal Buffer/Line Driver with 3-STATE OutputsElectrical CharacteristicsT = +25°CT = −40°C to +85°CA AVSymbol Parameter Units ConditionsCCMin Typ ..
74LVX240MX ,Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs74LVX240 Low Voltage Octal Buffer/Line Driver with 3-STATE OutputsMay 1993Revised October 200374LVX ..
74LVX244 ,LOW VOLTAGE OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)
74LVX244 ,LOW VOLTAGE OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)
74LVX244 ,LOW VOLTAGE OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)
74LVX244 ,LOW VOLTAGE OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)
855833 , 1880 MHz SAW Split Band Filter
855915 , 249.6 MHz SAW Filter
855924 , 881.5 MHz SAW Filter
855942 , 770 MHz SAW Filter
856158 , 183.6 MHz SAW Filter
856184 , 1220 MHz SAW Filter
74LVX240M-74LVX240MTC-74LVX240MX
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
74LVX240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs May 1993 Revised October 2003 74LVX240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The LVX240 is an octal inverting buffer and line driverInput voltage translation from 5V to 3V designed to be employed as a memory address driver,Ideal for low power/low noise 3.3V applications clock driver and bus oriented transmitter or receiver which Guaranteed simultaneous switching noise level and provides improved PC board density. The inputs tolerate dynamic threshold performance up to 7V allowing interface of 5V systems to 3V systems. Ordering Code: Order Number Package Number Package Description 74LVX240M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions IEEE/IEC Pin Names Description OE , OE 3-STATE Output Enable Inputs 1 2 I –I Inputs 0 7 O –O Outputs 0 7 Truth Tables Inputs Outputs OE I (Pins 12, 14, 16, 18) 1 n L L H L H L Connection Diagram H X Z Inputs Outputs OE I (Pins 3, 5, 7, 9) 2 n L L H L H L H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance © 2003 DS011609
