74LVX163MX ,Low Voltage Synchronous Binary Counter with Synchronous ClearGeneral Descriptionusing external gates.The LVX163 is a synchronous modulo-16 binary counter.The in ..
74LVX174 ,LOW VOLTAGE 3 TO 8 LINE DECODER (INV.) WITH 5V TOLERANT INPUTS
74LVX174 ,LOW VOLTAGE 3 TO 8 LINE DECODER (INV.) WITH 5V TOLERANT INPUTS
74LVX174M ,Low Voltage Hex D-Type Flip-Flop with Master ResetapplicationsThe information on the D inputs is transferred to storage
74LVX163MTC-74LVX163MTCX-74LVX163MX
Low Voltage Synchronous Binary Counter with Synchronous Clear
74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear October 1996 Revised October 2003 74LVX163 Low Voltage Synchronous Binary Counter with Synchronous Clear facilitates easy implementation of n-bit counters without General Description using external gates. The LVX163 is a synchronous modulo-16 binary counter. The inputs tolerate voltages up to 7V allowing the interface This device is synchronously presettable for application in of 5V systems to 3V systems. programmable dividers and has two types of Count Enable inputs plus a Terminal Count output for versatility in forming Features multistage counters. The CLK input is active on the rising edge. Both PE and MR inputs are active on low logic lev-Input voltage level translation from 5V to 3V els. Presetting is synchronous to rising edge of the CLK Ideal for low power/low noise 3.3V applications and the Clear function of the LVX163 is synchronous to the Guaranteed simultaneous switching noise and dynamic CLK. Two enable inputs (CEP and CET) and Carry Output threshold performance are provided to enable easy cascading of counters, which Ordering Code: Order Number Package Number Package Description 74LVX163M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX163SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX163MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Description Names CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input MR Synchronous Master Reset Input P –P Parallel Data Inputs 0 3 PE Parallel Enable Inputs Q –Q Flip-Flop Outputs 0 3 TC Terminal Count Output © 2003 DS012157
