74LVX161284A ,Low Voltage IEEE 161284 Translating TransceiverFeaturesThe LVX161284A contains eight bidirectional data buffers
74LVX161284A
Low Voltage IEEE 161284 Translating Transceiver
74LVX161284A Low Voltage IEEE 161284 Translating Transceiver June 1999 Revised June 2002 74LVX161284A Low Voltage IEEE 161284 Translating Transceiver General Description Features The LVX161284A contains eight bidirectional data buffersSupports IEEE 1284 Level 1 and Level 2 signaling and eleven control/status buffers to implement a full standards for bidirectional parallel communications IEEE 1284 compliant interface. The device supports the between personal computers and printing peripherals IEEE 1284 standard, with the exception of output slew rate, with the exception of output slew rate and is intended to be used in an Extended Capabilities PortTranslation capability allows outputs on the cable side to mode (ECP). The pinout allows for easy connection from interface with 5V signals the Peripheral (A-side) to the Host (cable side). All inputs have hysteresis to provide noise margin Outputs on the cable side can be configured to be either B and Y output resistance optimized to drive external open drain or high drive (± 14 mA) and are connected to a cable separate power supply pin (V cable) to allow these out- CC B and Y outputs in high impedance mode during power puts to be driven by a higher supply voltage than the A- down side. The pull-up and pull-down series termination resis- Inputs and outputs on cable side have internal pull-up tance of these outputs on the cable side is optimized to resistors drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resis-Flow-through pin configuration allows easy interface tors connected to the V cable supply to provide proper between the “Peripheral and Host” CC termination and pull-ups for open drain mode.Replaces the function of two (2) 74ACT1284 devices Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A –A /B –B transceiver 1 8 1 8 pins. Ordering Code Package Order Number Package Description Number 74LVX161284AMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 74LVX161284AMTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Connection Diagram Pin Descriptions Pin Names Description HD High Drive Enable Input (Active HIGH) DIR Direction Control Input A –A Inputs or Outputs 1 8 B –B Inputs or Outputs 1 8 A –A Inputs 9 13 Y –Y Outputs 9 13 A –A Outputs 14 17 C –C Inputs 14 17 PLH Peripheral Logic HIGH Input IN PLH Peripheral Logic HIGH Output HLH Host Logic HIGH Input IN HLH Host Logic HIGH Output © 2002 DS500204
