74LVX132MTCX ,Low Voltage Quad 2-Input NAND Schmitt TriggerElectrical CharacteristicsT
74LVX132MTC-74LVX132MTCX-74LVX132MX-74LVX132SJ
Low Voltage Quad 2-Input NAND Schmitt Trigger
74LVX132 Low Voltage Quad 2-Input NAND Schmitt Trigger October 1996 Revised February 2005 74LVX132 Low Voltage Quad 2-Input NAND Schmitt Trigger General Description Features The LVX132 contains four 2-input NAND Schmitt TriggerInput voltage level translation from 5V to 3V Gates. The pin configuration and function are the same asIdeal for low power/low noise 3.3V applications the LVX00 but the inputs have hysteresis between the pos- Guaranteed simultaneous switching noise level and itive-going and negative-going input thresholds, which are dynamic threshold performance capable of transforming slowly changing input signals into sharply defined, jitter-free output signals, thus providing greater noise margins than conventional gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. Ordering Code: Package Order Number Package Description Number 74LVX132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX132SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVX132MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Diagram Connection Diagram Pin Descriptions Pin Names Descriptions A , B Inputs n n Y Outputs n © 2005 DS012159
