74LVX126M ,LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTS74LVX126LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTS ■ HIGH SPEED: t =4.4ns ..
74LVX126TTR ,LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVX132 ,Low Voltage Quad 2-Input NAND Schmitt Trigger
74LVX132 ,Low Voltage Quad 2-Input NAND Schmitt Trigger
74LVX132M ,Low Voltage Quad 2-Input NAND Schmitt TriggerAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVX132MTC ,Low Voltage Quad 2-Input NAND Schmitt Triggerapplicationsthe LVX00 but the inputs have hysteresis between the pos-
74LVX126M-74LVX126TTR
LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTS
1/9July 2001 HIGH SPEED:
tPD=4.4ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL:
VIL = 0.8V, VIH = 2V at VCC =3V LOW POWER DISSIPATION:
ICC = 2 μA (MAX.) at TA=25°C LOW NOISE:
VOLP = 0.3V (TYP .) at VCC =3.3V SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4 mA (MIN) at VCC =3V BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 126 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVX126 is a low voltage CMOS QUAD
BUS BUFFERs fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This device requires the 3-STATE control input G
to be set low to place the output go in to the high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V. It combines high speed
performance with the true CMOS low power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX126LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE)
WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVX1262/9
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X :Don‘t Care
Z : High Impedance
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2.0V
74LVX1263/9
DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
74LVX1264/9
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per circuit)
74LVX1265/9
TEST CIRCUIT CL =15/50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74LVX1266/9
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
