74LVX125MTCX ,Low Voltage Quad Buffer with 3-STATE Outputsapplicationsto 7V allowing the interface of 5V systems to 3V systems.
74LVX125MTC-74LVX125MTCX-74LVX125MX-74LVX125SJ-74LVX125SJX
Low Voltage Quad Buffer with 3-STATE Outputs
74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs February 1994 Revised February 2005 74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs General Description Features The LVX125 contains four independent non-inverting buff-Input voltage level translation from 5V to 3V ers with 3-STATE outputs. The inputs tolerate voltages upIdeal for low power/low noise 3.3V applications to 7V allowing the interface of 5V systems to 3V systems. Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Package Order Number Package Description Number 74LVX125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX125SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVX125MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol Connection Diagram IEEE/IEC Truth Table Inputs Output Pin Descriptions OE A O n n n Pin Names Description LLL A Inputs n LH H OE Output Enable Inputs n HX Z O Outputs n H HIGH Voltage Level L LOW Voltage Level Z High Impedance X Immaterial © 2005 DS012007
