74LVX125 ,Low Voltage Quad Buffer with 3-STATE OutputsFeaturesThe LVX125 contains four independent non-inverting buff- Input voltage level translation f ..
74LVX125MTC ,Low Voltage Quad Buffer with 3-STATE OutputsFeaturesThe LVX125 contains four independent non-inverting buff-
74LVX125
Low Voltage Quad Buffer with 3-STATE Outputs
74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs February 1994 Revised March 1999 74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs General Description Features The LVX125 contains four independent non-inverting buff- � Input voltage level translation from 5V to 3V ers with 3-STATE outputs. The inputs tolerate voltages up � Ideal for low power/low noise 3.3V applications to 7V allowing the interface of 5V systems to 3V systems. � Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number Package Number Package Description 74LVX125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 74LVX125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Truth Table Inputs Output Pin Descriptions OE A O n n n Pin Names Description LLL A Inputs n LH H OE Output Enable Inputs n HX Z O Outputs H = HIGH Voltage Level n L = LOW Voltage Level Z = High Impedance X = Immaterial © 1999 DS012007.prf
