74LVTH16244 ,Low Voltage16-Bit Buffer/Line Driver with 3-STATE OutputsLOGIC DIAGRAMMAX at V =0Vto1.5V,V =1.5Vto0V,TCC CC A=85°C
74LVTH16244
LOW VOLTAGE BICMOS 16 BIT BUS BUFFER WITH BUS HOLDER AND POWER UP 3-STATE
1/13February 2004 HIGH SPEED:
tPD= 3.2ns (MAX.)atTA= 85°C VCC =3.0V LOW POWER DISSIPATION HIGH LEVEL
OUTPUT:ICC =190μA(MAX.)atTA= 85°C OUTPUT IMPEDANCE:OH|= 32mA,IOL= 64mA (MINatVCC =3.0V)OH|= 8mA,IOL= 24mA (MINatVCC =2.7V) BALANCED PROPAGATION DELAYS: PLH≅t PHL POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS COMPATIBLE WITH TTL OUTPUTS:IH =2V (MIN),VIL =0.8V(MAX)at
VCC= 2.7to 3.6V POWER-UP/DOWN 3-STATE:I OZPU= 100μA
MAXatVCC =0Vto 1.5V,VCC =1.5V to0V,TA=85°C BUS HOLD PROVIDED ON DATA INPUTS OPERATING VOLTAGE RANGE:CC (OPR)= 2.7Vto 3.6V PIN AND FUNCTION COMPATIBLE WITH SERIES H16244 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
DESCRIPTIONThe 74LVTH16244isa low voltage BiCMOS 16
BIT BUS BUFFER (NON-INVERTED) fabricated
with sub-micron silicon gate and five-layer metal
wiring BiCMOS technology.Itis ideal and full
specifiedfor hot-insertion and high speed 3.3V ap-
plications; the power-up/down 3-state circuitry
places the outputsin the high impedance state
during power-up/down, which prevents driver con-
flict. This functionis guaranteed when VCCis be-
tween0 and 1.5V.It canbe interfacedto 3.3V sig-
nal environment for both inputs and outputs. Any output control governs four BUS BUFFERS.
Output Enable input (nG) tied together gives full
16-bit operation. When nGis LOW, the outputs
are on. When nGis HIGH, the output arein high
impedance state effectively isolated. Bus hold on
data inputsis providedin orderto eliminate the
needfor external pull-upor pull-down resistors.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
ESD immunity and transient excess voltage.
74LVTH16244LOW VOLTAGE BICMOS 16 BIT BUS BUFFER
WITH BUS HOLD AND POWER UP 3-STATE
ORDER CODES
LOGIC DIAGRAM
74LVTH162442/13
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
74LVTH162443/13
PIN CONNECTION (top view for TSSOP, top through view for BGA)
TRUTH TABLE= High Impedance;X= Don’t care,n= 1..4,x=1..4
74LVTH162444/13
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device may occur. Functional operation under these conditionsis
not implied
(*) 500mW: ≅ 65°C deratedto 300mWby 10mW/°C: 65°Cto 85°C
RECOMMENDED OPERATING CONDITIONSVI from 0.8Vto 2.0Vat VCC =2.7Vto 3.6V
74LVTH162445/13
SPECIFICATIONS(*) Power Supply Range VCC =3.3±0.3V
74LVTH162446/13
ELECTRICAL CHARACTERISTICS Skewis definedasthe absolute valueofthe difference betweenthe actual propagation delayfor anytwo outputsofthe same device
switchinginthe same direction, either HIGHor LOW (tOSLH=| tPLHm -tPLHn|, tOSHL =|tPHLm -tPHLn| Parameter guaranteedby design
CAPACITANCE CHARACTERISTICS
TEST CIRCUIT= 50pFor equivalent (includesjig and probe capacitance) =R1 =500Ωor equivalent =ZOUTof pulse generator (typically 50Ω)
74LVTH162447/13
WAVEFORM SYMBOL VALUE
WAVEFORM1: PROPAGATION DELAY (f=1MHz; 50% duty cycle)
