74LVTH162373MTX ,Low Voltage 16-Bit Transparent Latch with 3-STATE Outputsapplications, but with the capability to provide a TTL inter-face to a 5V environment. The LVTH1623 ..
74LVTH162374 ,Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25-Ohm Series Resistors in the Outputsapplications, but with the capability to provide a TTL inter-Machine model > 200Vface to a 5V envir ..
74LVTH162374 ,Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25-Ohm Series Resistors in the Outputsapplications such asmake external termination resistors unnecessary andmemory address drivers, cloc ..
74LVTH162374 ,Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25-Ohm Series Resistors in the Outputsapplications. The device is byte controlled. A buff-
74LVTH162373MTX
Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs
74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25Ω Series Resistors in the Outputs October 2000 Revised November 2000 74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25Ω Series Resistors in the Outputs General Description Features The LVTH162373 contains sixteen non-inverting latchesInput and output interface capability to systems at with 3-STATE outputs and is intended for bus oriented 5V V CC applications. The device is byte controlled. The flip-flops Bushold data inputs eliminate the need for external appear transparent to the data when the Latch Enable (LE) pull-up resistors to hold unused inputs is HIGH. When LE is LOW, the data that meets the setup Live insertion/extraction permitted time is latched. Data appears on the bus when the Output Power Up/Down high impedance provides glitch-free Enable (OE) is LOW. When OE is HIGH, the outputs are in bus loading a high impedance state. Outputs include equivalent series resistance of 25Ω to The LVTH162373 is designed with equivalent 25Ω series make external termination resistors unnecessary and resistance in both the HIGH and LOW states of the output. reduce overshoot and undershoot This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceiv-Functionally compatible with the 74 series 16373 ers/transmitters. Latch-up performance exceeds 500 mA The LVTH162373 data inputs include bushold, eliminating ESD performance: the need for external pull-up resistors to hold unused Human-body model > 2000V inputs. Machine model > 200V These latches are designed for low-voltage (3.3V) V CC Charged-device model > 1000V applications, but with the capability to provide a TTL inter- face to a 5V environment. The LVTH162373 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Ordering Code: Package Order Number Package Description Number 74LVTH162373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide [TUBES] 74LVTH162373MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide (Note 1) [TAPE and REEL] 74LVTH162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBES] 74LVTH162373MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 1) [TAPE and REEL] Note 1: Use this Order Number to receive devices in Tape and Reel. Logic Symbol © 2000 DS500354
