74LVTH125MX ,Low Voltage Quad Buffer with 3-STATE OutputsFeaturesThe LVTH125 contains four independent non-inverting
74LVTH125M-74LVTH125MTC-74LVTH125MTCX-74LVTH125MX
Low Voltage Quad Buffer with 3-STATE Outputs
74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs October 1998 Revised February 2005 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs General Description Features The LVTH125 contains four independent non-invertingInput and output interface capability to systems at buffers with 3-STATE outputs. 5V V CC These buffers are designed for low-voltage (3.3V) VBushold data inputs eliminate the need for external CC applications, but with the capability to provide a TTL inter- pull-up resistors to hold unused inputs face to a 5V environment. The LVTH125 is fabricated withLive insertion/extraction permitted an advanced BiCMOS technology to achieve high speed Power Up/Down high impedance provides glitch-free operation similar to 5V ABT while maintaining a low power bus loading dissipation. Outputs source/sink 32 mA/64 mA Functionally compatible with the 74 series 125 Latch-up performance exceeds 500 mA ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model! 1000V Ordering Code: Package Order Number Package Description Number 74LVTH125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVTH125SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH125MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDED J-STD-020B). Device available in Tape and Reel only. © 2005 DS012011
