74LVTH125 ,Low Voltage Quad Buffer with 3-STATE Outputs74LVTH125 Low Voltage Quad Buffer with 3-STATE OutputsOctober 1998Revised November 200074LVTH125Low ..
74LVTH125 ,Low Voltage Quad Buffer with 3-STATE Outputsapplications, but with the capability to provide a TTL inter- pull-up resistors to hold unused inpu ..
74LVTH125 ,Low Voltage Quad Buffer with 3-STATE OutputsFeaturesThe LVTH125 contains four independent non-inverting
74LVTH125
Low Voltage Quad Buffer with 3-STATE Outputs
74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs October 1998 Revised November 2000 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs General Description Features The LVTH125 contains four independent non-invertingInput and output interface capability to systems at buffers with 3-STATE outputs. 5V V CC These buffers are designed for low-voltage (3.3V) V CCBushold data inputs eliminate the need for external applications, but with the capability to provide a TTL inter- pull-up resistors to hold unused inputs face to a 5V environment. The LVTH125 is fabricated withLive insertion/extraction permitted an advanced BiCMOS technology to achieve high speed Power Up/Down high impedance provides glitch-free operation similar to 5V ABT while maintaining a low power bus loading dissipation. Outputs source/sink −32 mA/+64 mA Functionally compatible with the 74 series 125 Latch-up performance exceeds 500 mA ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVTH125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74LVTH125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH125MTC MTC14 114-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Truth Table Pin Descriptions Inputs Output A B O n n n Pin Names Description LLL A , B Inputs n n LH H O 3-STATE Outputs n HX Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance © 2000 DS012011
