74LVTH573SJX ,Low Voltage Octal Transparent Latch with 3-STATE OutputsFunctional DescriptionThe LVT573 and LVTH573 contain eight D-type latches with 3-STATE standard out ..
74LVTH574 ,Low Voltage Octal D-Type Flip-Flop with 3-STATE OutputsFunctional DescriptionThe LVT574 and LVTH574 consist of eight edge-triggered Clock (CP) transition. ..
74LVTH574 ,Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputsapplications, but with the capability to provide a TTLCC
74LVT573MSA-74LVT573MTC-74LVT573WM-74LVTH573MTC-74LVTH573MTCX-74LVTH573SJ-74LVTH573SJX
Low Voltage Octal Transparent Latch with 3-STATE Outputs
74LVT573 • 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs March 1999 Revised November 2000 74LVT573 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVT573 and LVTH573 consist of eight latches with 3-Input and output interface capability to systems at STATE outputs for bus organized system applications. The 5V V CC latches appear transparent to the data when Latch Enable Bushold data inputs eliminate the need for external (LE) is HIGH. When LE is low, the data satisfying the input pull-up resistors to hold unused inputs (74LVTH573), timing requirements is latched. Data appears on the bus also available without bushold feature (74LVT573). when the Output Enable (OE) is LOW. When OE is HIGH, Live insertion/extraction permitted the bus output is in the high impedance state. Power Up/Down high impedance provides glitch-free The LVTH573 data inputs include bushold, eliminating the bus loading need for external pull-up resistors to hold unused inputs. Outputs source/sink −32 mA/+64 mA These octal latches are designed for low-voltage (3.3V) Functionally compatible with the 74 series 573 V applications, but with the capability to provide a TTL CC Latch-up performance exceeds 500 mA interface to a 5V environment. The LVT573 and LVTH573 are fabricated with an advanced BiCMOS technology toESD performance: achieve high speed operation similar to 5V ABT while Human-body model > 2000V maintaining a low power dissipation. Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVT573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74LVT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVT573MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LVT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74LVTH573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH573MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LVTH573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 2000 DS012450
