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74LVT573
3.3V Octal Transparent Latch with TRI-STATE(RM) Outputs
TL/F/12450
74LVT573
3.3V
ABT
Octal
Transparent
Latch
with
TRI-STATE
Outputs
PRELIMINARY
November 1996
74LVT573
3.3V ABT Octal Transparent Latch
with TRI-STATEÉ Outputs
General Description
The LVT573 consistsof eight latches with TRI-STATEout-
putsforbus organized system applications.The latchesap-
pear transparenttothe data when Latch Enable (LE)is
HIGH. WhenLEis low,the data satisfyingthe input timing
requirementsis latched. Data appearsonthebus whenthe
Output Enable (OE)is LOW. WhenOEis HIGH,thebus
outputisinthe high impedance state.
Theseoctallatches aredesignedfor low-voltage (3.3V)VCC
applications,but withthe capabilityto providea TTL inter-
facetoa5V environment.The LVT573is fabricated withan
advanced BiCMOS technologyto achieve high speed oper-
ation similarto5V ABT while maintainingalow power dissi-
pation.
Features Input and output interface capabilityto systemsat5V
VCC Bus-Hold data inputs eliminatethe needfor external
pull-up resistorsto hold unused inputs Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free
bus loading Outputs source/sink b32 mA/a64mA Availablein SOIC JEDEC, SOIC EIAJ, TSSOP and
SSOPII Functionally compatible withthe74 series573 Latch-up performance exceeds 500mA
Logic Symbols
TL/F/12450–1
IEEE/IEC
TL/F/12450–2
Connection Diagram
PinAssignmentfor
SOIC, TSSOP andSSOPII
TL/F/12450–3
Pin Names Description
D0–D7 Data Inputs Latch Enable Input OutputEnable Input
O0–O7 TRI-STATE Latch Outputs
SOIC JEDEC SOICEIAJ TSSOP SSOPII
Order Number 74LVT573WM 74LVT573SJ 74LVT573MTC 74LVT573MSA
74LVT573WMX 74LVT573SJX 74LVT573MTCX 74LVT573MSAX
SeeNS Package Number M20B M20D MTC20 MSA20
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1996National SemiconductorCorporation RRD-B30M17/Printed inU.S.A. http://
