74LVT374 ,3.3V ABT Octal D Flip-Flop with TRI-STATE Outputsapplications. A buff- Bus-Hold data inputs eliminate the need for externalered Clock (CP) and Outpu ..
74LVT374MTC ,Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputsapplications, but with the capability to provide a TTLCC
74LVT374
3.3V ABT Octal D Flip-Flop with TRI-STATE Outputs
TL/F/12016
74LVT374
3.3V
ABT
Octal
Flip-Flop
with
TRI-STATE
Outputs
ADVANCE INFORMATION
October 1995
74LVT374
3.3V ABT OctalD Flip-Flop with TRI-STATEÉ Outputs
General Description
The LVT374isa high-speed, low-power octal D-typeflip-
flop featuring separate D-type inputsfor each flip-flopand
TRI-STATE outputsfor bus-oriented applications.A buff-
ered Clock (CP)and Output Enable (OE)are commontoall
flip-flops.
These octal flip-flopsare designedfor low-voltage (3.3V)
VCC applications,but withthe capabilityto providea TTL
interfacetoa5V environment. The LVT374is fabricated
withan advanced BiCMOS technologyto achieve high
speed operation similarto5V ABT while maintainingalow
power dissipation.
Features Input and output interface capabilityto systemsat5V
VCC Bus-Hold data inputs eliminatethe needfor external
pull-up resistorsto hold unused inputs Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free
bus loading Outputs source/sink b32 mA/a64mA Availablein SOIC JEDEC, SOIC EIAJ, TSSOPand
SSOPII Functionally compatible withthe74 series374 Latch-up performance exceeds 500mA
Logic Symbols
TL/F/12016–1
IEEE/IEC
TL/F/12016–2
Connection Diagram
PinAssignmentfor
SOIC, TSSOPand SSOPII
TL/F/12016–3
Pin DescriptionNames
D0–D7 Data Inputs Clock Pulse Input TRI-STATE OutputEnable Input
O0–O7 TRI-STATE Outputs
SOIC JEDEC SOICEIAJ TSSOP JEDEC SSOPII
Order Number 74LVT374WM 74LVT374SJ 74LVT374MTC 74LVT374MSA
74LVT374WMX 74LVT374SJX 74LVT374MTCX 74LVT374MSAX
SeeNS Package Number M20B M20D MTC20 MSA20
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1996National SemiconductorCorporation RRD-B30M17/Printed inU.S.A. http://
