74LVT373MTCX ,Low Voltage Octal Transparent Latch with 3-STATE Outputsapplications, but with the capability to provide a TTLCCinterface to a 5V environment. The LVT373 a ..
74LVT373MTCX ,Low Voltage Octal Transparent Latch with 3-STATE Outputs74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE OutputsSeptember 1999Revised ..
74LVT374 ,3.3V ABT Octal D Flip-Flop with TRI-STATE Outputsapplications. A buff- Bus-Hold data inputs eliminate the need for externalered Clock (CP) and Outpu ..
74LVT374MTC ,Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputsapplications, but with the capability to provide a TTLCC
74LVT373MTC-74LVT373MTCX-74LVTH373MTCX-74LVTH373WM
Low Voltage Octal Transparent Latch with 3-STATE Outputs
74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs September 1999 Revised November 2000 74LVT373 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVT373 and LVTH373 consist of eight latches withInput and output interface capability to systems at 3-STATE outputs for bus organized system applications. 5V V CC The latches appear transparent to the data when Latch Bushold data inputs eliminate the need for external Enable (LE) is HIGH. When LE is LOW, the data satisfying pull-up resistors to hold unused inputs (74LVTH373), the input timing requirements is latched. Data appears on also available without bushold feature (74LVT373). the bus when the Output Enable (OE) is LOW. When OE is Live insertion/extraction permitted HIGH, the bus output is in a high impedance state. Power Up/Down high impedance provides glitch-free The LVTH373 data inputs include bushold, eliminating the bus loading need for external pull-up resistors to hold unused inputs. Outputs source/sink −32 mA/+64 mA These octal latches are designed for low-voltage (3.3V) Functionally compatible with the 74 series 373 V applications, but with the capability to provide a TTL CC interface to a 5V environment. The LVT373 and LVTH373ESD performance: are fabricated with an advanced BiCMOS technology to Human-body model > 2000V achieve high speed operation similar to 5V ABT while Machine model > 200V maintaining low power dissipation. Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVTH373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Logic Symbols IEEE/IEC © 2000 DS012015
