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74LVT16500
3.3 Volt ABT 18-Bit Universal Bus Transceivers with TRI-STATE Outputs
TL/F/12447
74LVT16500
3.3V
ABT
18-Bit
Universal
Bus
Transceivers
with
TRI-STATE
Outputs
ADVANCE INFORMATION
October 1995
74LVT16500
3.3V ABT 18-Bit Universal Bus Transceivers
with TRI-STATEÉ Outputs
General Description
The LVT16500 consistof eighteen universalbus transceiv-
ers combine D-type latches and D-type flip-flopsto allow
data flowin transparent, latched,and clocked modes.
Data flowin each directionis controlledby output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKABand CLKBA) inputs.For A-to-B data flow,the
device operatesinthe transparent mode when LEABis
high. When LEABis low,theA datais latchedif CLKABis
heldata highorlow logic level.If LEABis low,theAbus
datais storedinthe latch/flip-floponthe high-to-low tran-
sitionof CLKAB. Output-enable OEABis active-high. When
OEABis high,the outputsare active. When OEABis low,
the outputsareinthe high-impedance state.
Data flowforBtoAis similarto thatofAtoBbut uses
OEBA, LEBA,and CLKBA. The output enablesare comple-
mentary (OEABis active highand OEBAis active low).
The transceiversare designedfor low-voltage (3.3V) VCC
applications,but withthe capabilityto providea TTL inter-
facetoa5V environment.The LVT16500is fabricated with advanced BiCMOS technologyto achieve high speed
operation similarto5V ABT while maintainingalow power
dissipation.
Features Input and output interface capabilityto systemsat5V
VCC Bus-Hold data inputs eliminatethe needfor external
pull-up resistorsto hold unused inputs Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free
bus loading Outputs source/sink b32 mA/a64mA Availablein SSOPand TSSOP Functionally compatible withthe74 series 16500 Latch-up performance exceeds 500mA
Pin Description
PinNames Description
A0–A17 Data RegisterA Inputs/TRI-STATE
Outputs
B0–B17 Data RegisterB Inputs/TRI-STATE
Outputs
CLKAB,CLKBA ClockPulseInputs
LEAB,LEBA Latch Enable Inputs
OEAB, OEBA Output EnableInputs
SSOP EIAJ TSSOP
Order Number 74LVT16500MEA 74LVT16500MTD
74LVT16500MEAX 74LVT16500MTDX Package MS56A MTD56Number
Connection Diagram
Pin Assignmentfor SSOP andTSSOP
TL/F/12447–1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1996National SemiconductorCorporation RRD-B30M17/Printed inU.S.A. http://
