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74LVT125
3.3V ABT Quad Buffer with TRI-STATE Outputs
TL/F/12011
74LVT125
3.3V
ABT
Quad
Buffer
with
TRI-STATE
Outputs
PRELIMINARY
November 1996
74LVT125
3.3V ABT Quad Buffer with TRI-STATEÉ Outputs
General Description
The LVT125 contains four independent non-inverting buff-
ers with TRI-STATE outputs.
These buffersare designedfor low-voltage (3.3V) VCCap-
plications,but withthe capabilityto providea TTL interfacea5V environment. The LVT125is fabricated withanad-
vanced BiCMOS technologyto achieve high speed opera-
tion similarto5V ABT while maintainingalow power dissi-
pation.
Features Inputand output interface capabilityto systemsat5V
VCC Bus-Hold data inputs eliminatethe needfor external
pull-up resistorsto hold unused inputs Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free
bus loading Outputs source/sink b32 mA/a64mA Availablein SOIC JEDEC, SOIC EIAJ,and TSSOP Functionally compatible withthe74 series125 Latch-up performance exceeds 500mA
Logic Symbol
IEEE/IEC
TL/F/12011–1
Connection Diagram
Pin Assignmentfor
SOIC andTSSOP
TL/F/12011–2
Pin Names Description
An,Bn Inputs TRI-STATE Outputs
Truth Table
Inputs Output Bn On L H Ze HIGH VoltageLeveleLOW VoltageLevele HIGHImpedancee Immaterial
SOIC JEDEC SOICEIAJ TSSOP
Order Number 74LVT125M 74LVT125SJ 74LVT125MTC
74LVT125MX 74LVT125SJX 74LVT125MTCX
SeeNS PackageNumber M14A M14D MTC14
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1996National SemiconductorCorporation RRD-B30M17/Printed inU.S.A. http://
