74LVQ74 ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVQ74M ,DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEARapplications.CCA signal on the D INPUT is transferred to the Q■ PIN AND FUNCTION COMPATIBLE WITH OU ..
74LVQ74SC ,Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop74LVQ74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-FlopFebruary 1992Revised June 200174LV ..
74LVQ74SCX ,Low Voltage Dual D-Type Positive Edge-Triggered Flip-FlopapplicationsClear and Set inputs and complementary (Q, Q) outputs.
74LVQ74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
1/13July 2004 HIGH SPEED:
fMAX = 250 MHz (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION:
ICC =2 μA (MAX.) at TA=25°C LOW NOISE:OLP = 0.2 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3.0V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVQ74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and low noise
3.3V applications.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ74DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 5
74LVQ742/13
Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description
Table 3: Truth Table X : Don’t Care
Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays
74LVQ743/13
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
Table 6: DC Specifications 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
74LVQ744/13
Table 7: Dynamic Switching Characteristics 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
Table 8: AC Electrical Characteristics (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
74LVQ745/13
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
Figure 4: Test Circuit CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74LVQ746/13
Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)
74LVQ747/13
Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Pulse Width
