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74LVQ374SC
Low Voltage Octal D Flip-Flop with 3-STATE Outputs
74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs February 1992 Revised June 2001 74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The LVQ374 is a high-speed, low-power octal D-type flip-Ideal for low power/low noise 3.3V applications flop featuring separate D-type inputs for each flip-flop andImplements patented EMI reduction circuitry 3-STATE outputs for bus-oriented applications. A buffered Available in SOIC JEDEC, SOIC EIAJ and QSOP pack- Clock (CP) and Output Enable (OE) are common to all flip- ages flops. Guaranteed simultaneous switching noise level and dynamic threshold performance Improved latch-up immunity Guaranteed incident wave switching into 75Ω 4 kV minimum ESD immunity Buffered positive edge-triggered clock 3-STATE outputs drive bus lines or buffer memory address registers Ordering Code: Order Number Package Number Package Description 74LVQ374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ374QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Truth Table Inputs Outputs Pin Descriptions D CP OE O n n Pin Names Description HLH D –D Data Inputs LLL 0 7 CP Clock Pulse Input XX H Z H = HIGH Voltage Level L = LOW Voltage Level OE 3-STATE Output Enable Input X = Immaterial Z = High Impedance O –O 3-STATE Outputs 0 7 = LOW-to-HIGH Transition © 2001 DS011360
