74LVQ373QSCX ,Low Voltage Octal Transparent Latch with 3-STATE Outputsapplications. The latches
74LVQ373QSC-74LVQ373QSCX-74LVQ373SCX
Low Voltage Octal Transparent Latch with 3-STATE Outputs
74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs February 1992 Revised June 2001 74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVQ373 consists of eight latches with 3-STATE out-Ideal for low power/low noise 3.3V applications puts for bus organized system applications. The latchesImplements patented EMI reduction circuitry appear transparent to the data when Latch Enable (LE) is Available in SOIC JEDEC, SOIC EIAJ and QSOP HIGH. When LE is low, the data satisfying the input timing packages requirements is latched. Data appears on the bus when the Guaranteed simultaneous switching noise level and Output Enable (OE) is LOW. When OE is HIGH, the bus dynamic threshold performance output is in the high impedance state. Improved latch-up immunity Guaranteed incident wave switching into 75Ω 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74LVQ373SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ373QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Truth Table Inputs Outputs Pin Descriptions LE OE D O n n XH X Z Pin Names Description HL L L D –D Data Inputs 0 7 HL H H LE Latch Enable Input LL X O 0 OE Output Enable Input H = HIGH Voltage Level L = LOW Voltage Level O –O 3-STATE Latch Outputs 0 7 Z = High Impedance X = Immaterial O = Previous O before HIGH to Low transition of Latch Enable 0 0 © 2001 DS011359
