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74LVQ373M-74LVQ373TTR
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTING
1/10July 2001 HIGH SPEED:
tPD = 5.8 ns (TYP .) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION:
ICC = 4 μA (MAX.) at TA=25°C LOW NOISE:
VOLP = 0.4V (TYP .) at VCC = 3.3V 75Ω TRANSMISSION LINE OUTPUT DRIVE
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVQ373 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely .
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ373LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVQ3732/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care;
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low logic level
LOGIC DIAGRAM
74LVQ3733/10
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
74LVQ3734/10
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
74LVQ3735/10
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Latch)
74LVQ3736/10
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
