74LVQ32TTR ,QUAD 2-INPUT OR GATEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVQ373 ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTING
74LVQ373M ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT NON INVERTINGAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVQ373QSC ,Low Voltage Octal Transparent Latch with 3-STATE Outputs74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE OutputsFebruary 1992Revised June 200174LV ..
74LVQ373QSCX ,Low Voltage Octal Transparent Latch with 3-STATE Outputsapplications. The latches
74LVQ32M-74LVQ32TTR
QUAD 2-INPUT OR GATE
1/8July 2001 HIGH SPEED:
tPD = 5.2 ns (TYP .) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION:
ICC = 2μA (MAX.) at TA=25°C LOW NOISE:
VOLP = 0.3V (TYP .) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 12mA (MIN) at VCC = 3.0V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 32 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVQ32 is a low voltage CMOS QUAD
2-INPUT OR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 2 stages
including buffer output, which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ32LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVQ322/8
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
74LVQ323/8
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
74LVQ324/8
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74LVQ325/8
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
