74LVQ280M ,8 BIT PARITY GENERATORAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVQ32M ,QUAD 2-INPUT OR GATEapplications.74 SERIES 32 The internal circuit is composed of 2 stagesincluding buffer output, whic ..
74LVQ32SC ,Low Voltage Quad 2-Input OR Gate74LVQ32 Low Voltage Quad 2-Input OR GateFebruary 1992Revised June 200174LVQ32Low Voltage Quad 2-Inp ..
74LVQ32SCX ,Low Voltage Quad 2-Input OR Gateapplications
74LVQ280M
8 BIT PARITY GENERATOR
1/8July 2001 HIGH SPEED: PD = 8 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION:CC = 2μA(MAX.) at TA =25°C LOW NOISE:OLP = 0.3V (TYP .) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 3.6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVQ280 is a low voltage CMOS 9 BIT
PARITY GENERATOR fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and low noise
3.3V applications.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (ΣODD and ΣEVEN). The nine
data inputs control the output conditions. When
the number of high level input is odd, ΣODD
output is kept high and ΣEVEN output low.
Conversely, when the number of high level is
even, ΣEVEN output is kept high and ΣODD low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easily expanded by cascading.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ2809 BIT PARITY GENERATOR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVQ2802/8
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
LOGIC DIAGRAM
74LVQ2803/8
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
74LVQ2804/8
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
74LVQ2805/8
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
