74LVQ240SCX ,Low Voltage Octal Buffer/Line Driver with 3-STATE Outputsapplicationsdesigned to be employed as a memory address driver,
74LVQ240SCX
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs June 1993 Revised June 2001 74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The LVQ240 is an inverting octal buffer and line driverIdeal for low power/low noise 3.3V applications designed to be employed as a memory address driver,Implements patented EMI reduction circuitry clock driver and bus oriented transmitter or receiver which Available in SOIC JEDEC, SOIC EIAJ, and QSOP pack- provides improved PC board density. ages Guaranteed simultaneous switching noise level and dynamic threshold performance Improved latch-up immunity Guaranteed incident wave switching into 75Ω 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74LVQ240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ240QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description IEEE/IEC OE , OE 3-STATE Output Enable Inputs 1 2 I –I Inputs 0 7 O –O Outputs 0 7 Truth Tables Inputs Outputs OE I (Pins 12, 14, 16, 18) 1 n LL H Connection Diagram LH L HX Z Inputs Outputs OE I (Pins 3, 5, 7, 9) 2 n LL H LH L HX Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance © 2001 DS011611
