74LVQ240SC ,Low Voltage Octal Buffer/Line Driver with 3-STATE OutputsapplicationsThe LVQ240 is an inverting octal buffer and line driver de-signed to be employed as a m ..
74LVQ240SCX ,Low Voltage Octal Buffer/Line Driver with 3-STATE Outputsapplicationsdesigned to be employed as a memory address driver,
74LVQ240SC
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
74LVQ240
Low Voltage Octal Buffer/Line Driver with 3-STATE
Outputs
General DescriptionThe LVQ240isan inverting octal buffer andline driverde-
signedtobe employedasa memory address driver, clock
driver andbus oriented transmitteror receiver which pro-
vides improvedPC board density.
Features Idealforlow power/low noise 3.3V applications Implements patented EMI reduction circuitry Availablein SOIC JEDEC, SOIC EIAJ,and QSOP
packages Guaranteed simultaneous switching noise leveland
dynamic threshold performance Improved latch-up immunity Guaranteed incident wave switchinginto 75Ω4kV minimum ESD immunity
Ordering Code:
Order Number Package Number Package Description74LVQ240SC M20B 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
74LVQ240SJ M20D 20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
74LVQ240QSC MQA20 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC
Devicesalso availableinTapeand Reel.Specifyby appendingsuffixletter“X” tothe ordering code.
Logic Symbol
Pin Descriptions
Pin Names DescriptionOE1,OE2 3-STATE Output Enable Inputs
I0–I7 Inputs
O0–O7 Outputs
Connection Diagram
Truth Tables
Inputs Outputs
OE1 In (Pins12,14,16,18) H L Z
Inputs Outputs
OE2 In (Pins3,5,7,9) H L Z= HIGH Voltage LevelL= LOW Voltage Level= Immaterial Z=High Impedance
IEEE/IECDS011611-1
Pin Assignment,
SOICand QSOPDS011611-2
May 1998
74L
VQ240
Low
oltage
Octal
Buffer/Line
Driver
with
3-ST
Outputs©1998 DS011611
