74LVQ157TTR ,LOW VOLTAGE QUAD 2-CHANNEL MULTIPLEXERapplications.PIN CONNECTION AND IEC LOGIC SYMBOLSJuly 2001 1/874LVQ157INPUT AND OUTPUT EQUIVALENT C ..
74LVQ20M ,DUAL 4-INPUT NAND GATEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVQ240 ,LOW VOLTAGE OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)
74LVQ240 ,LOW VOLTAGE OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)
74LVQ240 ,LOW VOLTAGE OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)
74LVQ240M ,LOW VOLTAGE OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)applications.74 SERIES 240 G output control governs four BUS BUFFERs.This device is designed to be ..
82S100/BXA , Field Programmable Logic Array
82S131 ,2K-bit TTL bipolar PROM
83021012A ,8-Bit Universal Shift/Storage Registers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
83021AMILF , 1-TO-1 DIFFERENTIAL- TO-LVCMOS/LVTTL TRANSLATOR
8302401EA ,8302401EA · Hermetically Sealed, Low IF, Wide Vcc, High Gain OptocouplersfeaturesLife Critical Systems an open collector output providingThe connection of a 0.1 μF bypass c ..
83026AIL , LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
74LVQ157M-74LVQ157TTR
LOW VOLTAGE QUAD 2-CHANNEL MULTIPLEXER
1/8July 2001 HIGH SPEED:
tPD = 7 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION:
ICC = 4 μA (MAX.) at TA=25°C LOW NOISE:
VOLP = 0.2V (TYP .) at VCC = 3.3V 75Ω TRANSMISSION LINE OUTPUT DRIVE
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 157 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVQ157 is a low voltage CMOS QUAD
2-CHANNEL MULTIPLEXER fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology. It is ideal for low power
and low noise 3.3V applications.
It consists of four 2-input digital multiplexers with
common select and strobe inputs. When STROBE
input is held high selection of data is inhibit and all
the outputs become low. The SELECT decoding
determines whether the A or B inputs get routed to
their corresponding Y outputs.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ157LOW VOLTAGE QUAD 2 CHANNEL MULTIPLEXER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVQ1572/8
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
74LVQ1573/8
DC SPECIFICATIONS 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
74LVQ1574/8
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per
channel)
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74LVQ1575/8
WAVEFORM 1 : PROPAGATION DELAYS FOR NON INVERTING CONDITIONS
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING CONDITIONS
