74LVQ138 ,3 TO 8 LINE DECODER (INVERTING)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
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74LVQ138
3 TO 8 LINE DECODER (INVERTING)
1/12July 2004 HIGH SPEED:
tPD = 5.5ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION:
ICC = 4 μA (MAX.) at TA=25°C LOW NOISE:
VOLP = 0.2V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVQ138 is a low voltage CMOS 3 TO 8
LINE DECODER (INVERTING) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology. It is ideal for low power
and low noise 3.3V applications.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ1383 TO 8 LINE DECODER (INVERTING)
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 5
74LVQ1382/12
Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description
Table 3: Truth Table X : Don’t Care
Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays
74LVQ1383/12
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
Table 6: DC Specifications 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
74LVQ1384/12
Table 7: Dynamic Switching Characteristics 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
Table 8: AC Electrical Characteristics (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
74LVQ1385/12
Figure 4: Test Circuit CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 5: Waveform - Propagation Delays For Inverting Outputs (f=1MHz; 50% duty cycle)
74LVQ1386/12
Figure 6: Waveform - Propagation Delays For Non-inverting Outputs (f=1MHz; 50% duty cycle)
